
// DFF
module dff
#(
	parameter DW = 1
)(
	input 		    	 clk,
	input 		    	 en,
	input [DW-1:0]  	 d,
	output logic[DW-1:0] q
);

always @(posedge clk) begin
	if(en)
		q <= d;
end

endmodule

module dffr
#(
	parameter DW = 1,
	parameter DV = 0
)(
	input 		    	 clk,
	input 				 rst_n,
	input 		    	 en,
	input [DW-1:0]  	 d,
	output logic[DW-1:0] q
);

always @(posedge clk or negedge rst_n) begin
	if(~rst_n)
		q <= DV;
	else if(en)
		q <= d;
end
	
endmodule

module rob_id_cmpo #( //compare older
	parameter DW = 5
) (
	input [DW-1:0]			a,
	input [DW-1:0]			b,
	output 					res 
);
	
assign res = a[DW-1] == b[DW-1] ? a[DW-2:0] < b[DW-2:0] : a[DW-2:0] > b[DW-2:0];

endmodule

module rob_id_cmpy #( //compare older
	parameter DW = 5
) (
	input [DW-1:0]			a,
	input [DW-1:0]			b,
	output 					res 
);
	
assign res = a[DW-1] == b[DW-1] ? a[DW-2:0] > b[DW-2:0] : a[DW-2:0] < b[DW-2:0];

endmodule
